This invention relates to a clocking system, and more particularly, to a device and method that reduce jitter and generate clock signals.
Read, write, and servo channels used in hard drives can require three different clock sources. A read and write head can require separate clock signals to transform electrical signals into magnetic signals and magnetic signals into electrical signals, respectively. A servo can require a separate clock signal to accurately position a head on or above a surface of a hard drive platter. In each of these systems, the clock pulses are very high frequency clock pulses.
Clock management of read, write, and servo channels can be handled by multiple clock synthesizers that have a programmable output frequency over a wide bandwidth. One operational concern of some multiple clock synthesizers is the large amount of power these synthesizers can consume when distributing timing pulses. Multiple clock synthesizers having a large programmable frequency bandwidth can use multiple pairs of transistors that require high voltage biases to achieve high operating frequencies. Moreover, some oscillators contained within clock synthesizers can introduce and accumulate phase error. The phase error can degrade the performance of some clock synthesizers.